This invention relates to a semiconductor memory device formed of an integrated circuit of an insulated-gate field effect type known as an MOS integrated circuit and, more particularly, to a semiconductor memory device comprising memory cells of the surface-charge type.
Ever since MOS elements have been used successfully as memory cells, a continued problem has been to increase the memory capacity of a memory device formed on a semiconductor chip. Attempts have therefore been made to increase the bit density of the memory device by reducing the number of circuit elements of a unit memory cell while simplifying the structure of the circuit elements. So far, a one-transistor cell, such as the one described later is a unit memory cell consisting of the least possible number of elements. A surface-charge memory cell has been developed developed to achieve a further increased bit density. The latter memory cell, however, is complicated in structure and is more difficult to manufacture. As a result, the conventional surface-charge memory device is poorer in yield and reliability than the sophisticated one-transistor-cell memory device.